With the advent of multiplexed digital data communication systems the need for a frame synchronizer became apparent. In order to properly demultiplex the received signal the receiver must be operating synchronously with the transmitter. Thus, the prior art has been concerned with the design and operation of frame synchronizers since at least 1950, see U.S. Pat. No. 2,527,650. That patent relates to a frame synchronizer which is adapted to identify the framing bits in a serial data stream when the framing bits alternate in succeeding frames. That is, if the framing bit in one frame is a 1 the framing bit in the corresponding bit position of the succeeding frame will be a 0. The apparatus in that patent compared the quantity transmitted in a bit position with the quantity transmitted in the corresponding bit position of the next immediately following frame. So long as the quantities alternate in magnitude the bit position was considered a candidate for the framing bit. However, when two frames were detected in which the quantity transmitted in that bit position were the same, the apparatus determined that this bit position was no longer a candidate for the framing bit. In that case, a similar process was performed on an adjacent bit position. In this manner each bit position in the frame was examined until the framing bit position was located.
One drawback to this arrangement was the amount of time consumed in searching for the framing bit position. Andrews Jr., in U.S. Pat. No. 2,949,503, disclosed a frame synchronizer which improved, to some extent, the time consumed in identifyig the framing bit position.
Cirillo and Thovson in an article entitled "Digital Functions" appearing in the Bell System Technical Journal, Vol. 51, No. 8 (October 1972) at pp 1701-1712 disclose a further improvement in frame synchronizing circuits. See especially pp 1705-1708. Instead of examining a single bit position at a time, the Cirillo et al circuit monitors eight bit positions of a frame.
The present invention seeks to further improve the operation of frame synchronizers by reducing the time required for identifying the framing bit.
In addition, the invention also improves the operation of frame synchronizers in that the circuit complexity is reduced.
Furthermore, since the prior art frame synchronizers, referred to above, "look" at one, two or a plurality of bit positions (less than all bit positions), simultaneously, some convention must be adopted as to when a particular bit position is considered the framing bit. That is, it is of course possible for data bit positions to alternate in the quantity transmitted, from frame to frame. So long as the data transmitted in any bit position continues to alternate it will "look like" a framing bit. Therefore, for instance, Cirillo et al accept a particular bit position as the framing bit if the alternating pattern persists for about 2.5 milliseconds. Of course, while this may actually be the framing bit, it is also possible for this to be merely a data bit which has alternated in succeeding frames for this predetermined period of time. It is therefore another object of the present invention to select, as the framing bit, only the single bit in the frame which continues to illustrate the alternating pattern while each of the other bits has violated the alternating pattern at least once.